1. Field of the Invention
This invention relates to a semiconductor integrated circuit of a memory integrated circuit or the like, and more particularly to an intermediate potential setting circuit for setting the output potential of a data output circuit to an intermediate potential level immediately before the output of data.
2. Description of the Related Art
FIG. 5 shows an example of a data output circuit of semiconductor integrated circuit 40, a power source system and an output load. In FIG. 5, M1 and M2 denote data output MOS transistors, G1 and G2 data output control gates, N1 a data output terminal, N2 a power source terminal in a chip, N3 a ground terminal in the chip, E a D.C. power source for supplying a VDD power source voltage to the chip, C2 a voltage stabilizing capacitor, and C1 an output load capacitor. Wiring sections arranged inside and outside the chip have resistors R1 to R5 and impedance elements L1 to L3 as parasitic elements.
In the above data output circuit, power source potential VDD and ground potential VSS inside the chip will vary (or output noise occurs) in a case where output load C1 is rapidly charged or discharged at the data output time, causing the internal circuit of the semiconductor integrated circuit to be erroneously operated. Now, the operation of the circuit of FIG. 5 in which data output changes from "0" to "1" is explained with reference to FIGS. 6A and 6B. When output control signal .phi.out is set to "1" level while complementary data d and d are respectively kept at "1" and "0", output nodes N4 and N5 of gates G1 and G2 are respectively set into "1" and "0" states. As a result, output node N1 is set to "1" level, and transistor M1 is turned on, thus charging output load C1. At this time, the potentials of power source terminals N2 and N3 in the chip will vary due to the voltage drop occurring in parasitic elements R1, R2, R4, L1 and L2 associated with a current path in which charging current Id flows. In particular, when data "1" are simultaneously output at a plurality of data output terminals and corresponding data output terminals, the power source potential varies significantly so that the internal circuit of the input buffer or the like may tend to be erroneously operated.
In contrast, when the data output varies from "1" to "0", output load C1 is discharged. At this time, the ground potential in the chip and the power source potential in the chip may vary by the discharging current and said parasitic elements, causing the same problem as described above.
Typically, in order to suppress the power source potential variation at the time of change of data output, the gate widths of output MOS transistors M1 and M2 are reduced or the rising rate of the gate potential of output MOS transistors M1 and M2 is reduced as shown by broken lines in FIG. 6A. In this way, the current driving abilities of output MOS transistors M1 and M2 are reduced so that the potential of output terminal N1 can be smoothly changed. However, in this case, the rising time will be delayed by td, significantly affecting the high speed characteristic (access time in the case of memory integrated circuit) of the semiconductor integrated circuit.
Further, in order to suppress the power source potential variation at the time of change of output data, the following method has been proposed. In this method, an intermediate potential setting circuit for creating an intermediate potential level of the power source potential and a switching circuit are provided to set an intermediate potential between the power source potential and the ground potential. The switching circuit is turned on immediately before the data output so as to supply the intermediate potential output of the intermediate potential setting circuit to the output node of the data output circuit, thus previously setting the output node to the intermediate potential.
However, the above method has a disadvantage that the current consumption will be large if a resistor dividing circuit is used as the intermediate potential setting circuit. To avoid an increase of power consumption, it may be proposed that the current flowing through the resistor dividing circuit to preset an intermediate potential be limited. If the current is limited, however, it will take longer to preset the intermediate potential.